1. Field of the Invention
The present invention relates to an A/D converter that causes a quantizer to quantize a difference between an analog input signal and a predicted value output from a prediction filter to convert the analog input signal to a digital signal, and a sensor apparatus including the A/D converter.
2. Description of the Related Art
As this type of A/D converter, an oversampling A/D converter is disclosed in Japanese Unexamined Patent Application Publication No. 2003-318736, for example. This oversampling A/D converter is defined by a hybrid modulator 12 whose schematic configuration is illustrated in FIG. 1A. The hybrid modulator 12 uses both Δ (delta) modulation performed by a Δ modulator 1 illustrated in FIG. 1B and ΔΣ (delta sigma) modulation performed by a ΔΣ modulator. The Δ modulator 1 illustrated in FIG. 1B causes a delay device 3 to delay an output of a quantizer 2 by one sampling time, and causes a prediction filter 4 to integrate the output and to output, as a predicted value, the resultant output to an adder 5. At this time, the predicted value is converted to an analog signal by a D/A converter, which is not illustrated, and is output to the adder 5. The adder 5 outputs a difference between an input signal and the predicted value to the quantizer 2. The quantizer quantizes the input signal in accordance with a value of a threshold every time a sampling clock is input. The ΔΣ modulator has a configuration in which the prediction filter 4 and the adder 5 are removed from the hybrid modulator 12 illustrated in FIG. 1A. The ΔΣ modulator causes an adder 7 to calculate a difference between a signal obtained by causing the delay device 3 to delay an output of the quantizer 2 by one sampling time and an input signal. The difference is integrated in discrete time by an integrator 6 so as to be subjected to noise shaping so that a quantization noise spectrum increases in a high-frequency region, and is then quantized by the quantizer 2.
The hybrid modulator 12 causes the prediction filter 4 to integrate a signal obtained by causing the delay device 3 to delay an output of the quantizer 2 to generate a predicted value, and causes the adder 5 to calculate a difference between an input signal and the predicted value. Then, the ΔΣ modulation is performed on the difference. That is, the adder 7 takes a difference between a signal obtained by causing the delay device 3 to delay an output of the quantizer 2 and an output of the adder 5, and the difference is integrated by the integrator 6 and is quantized by the quantizer 2.
In the hybrid modulator 12 disclosed in Japanese Unexamined Patent Application Publication No. 2003-318736, when a difference determination device 13 detects that a difference output from the adder 5 has exceeded a threshold, a switch SW1 is switched to a terminal side to put a switch SW2 into an open state. Thus, the hybrid modulator 12 illustrated in FIG. 1A changes to the Δ modulator 1 illustrated in FIG. 1B. Even when an input signal with a large step that causes a slope overload on a Δ modulation unit is input, switching to the Δ modulator 1 is performed after one clock of an oversampling clock, and thus ringing does not occur.
The hybrid modulator 12 has the advantage of the Δ modulator 1 and the advantage of the ΔΣ modulator. The hybrid modulator 12 increases an input voltage range through Δ modulation, and also forces quantization noise to a high-frequency side through noise shaping in ΔΣ modulation to reduce quantization noise in a necessary signal band. An output of the hybrid modulator 12 is the derivative of an input, and thus, in the case in which the A/D converter is actually used, a post filter 14 for reproduction is necessary at a stage subsequent to the hybrid modulator 12 as illustrated in FIG. 1A. With respect to the output of the hybrid modulator 12 that have been integrated by the post filter 14, quantization noise outside the signal band is further isolated by a post filter, which is not illustrated.
Furthermore, as a ΔΣ modulator that performs noise shaping of quantization noise, a second-order low-pass ΔΣ modulator of a continuous time system is disclosed in Japanese Unexamined Patent Application Publication No. 2010-263483. In this ΔΣ modulator as well, quantization noise generated by a quantizer is subjected to noise shaping to be shifted to a high-frequency region, and a high SN ratio is obtained in a signal band.
In the existing A/D converter disclosed in Japanese Unexamined Patent Application Publication No. 2003-318736 defined by the hybrid modulator 12, the post filter 14 is necessary at a stage subsequent to the hybrid modulator 12 as described above. Furthermore, in the A/D converter defined by the Δ modulator 1 as well, an output is similarly the derivative of an input, and thus, the post filter 14 for reproduction is necessary at a stage subsequent to the Δ modulator 1 as illustrated in FIG. 1B. For this reason, in the existing A/D converter, the circuit size has been increased by the size of the post filter 14 for reproduction that is necessary.
Furthermore, in the existing A/D converter disclosed in Japanese Unexamined Patent Application Publication No. 2003-318736 and the ΔΣ modulator disclosed in Japanese Unexamined Patent Application Publication No. 2010-263483, quantization noise is shifted to a high-frequency region through noise shaping, and thus, a steep filter characteristic is demanded of a post filter necessary at a subsequent stage to isolate quantization noise outside a signal band. For this reason, in the existing A/D converter using noise shaping, the integrator 6 for noise shaping becomes necessary, and, in addition, the post filter has to be configured to have a steep filter characteristic, thereby resulting in an increase in circuit size.
Furthermore, in a sensor apparatus including the existing A/D converter disclosed in Japanese Unexamined Patent Application Publication No. 2003-318736, the input impedance of the adder 5 has to be substantially higher than the output impedance of an input signal source. For this reason, in the case in which a capacitive charge output element serves as the input signal source, the impedance of the charge output element itself is high, and thus, an impedance conversion circuit has to be provided between the charge output element and the adder 5. Furthermore, to detect an output of the capacitive charge output element, an amplifier becomes necessary for duplication and addition of electric charge in the integrator 6, and driving of the amplifier increases the power consumption of the A/D converter.